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Block-level layout guidelines


• Import from the chip level, the block size and port positions and try to stick
to them.
• Define feed-through signals so the overall chip congestion inside interblock
channels will be reduced.
• Define power needs and grid inside each block.
• Define critical path design and group the related cells to minimize routing.
• Plan for changes by having spare logic and lines.
• Try to improve efficiency by using automated tools. When the number of
components is 100 or more, even a good layout designer will find it hard to
respect all the design constraints for this many instances and still be fast.
Even if the tool is providing 80 percent of the job, it is much faster and
less prone to error if the designer uses assisted routing rather than hand
connectivity.





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