basic knowledge for a layout designer

The layout engineer should have

• Detailed knowledge of the entire set of layers and layout design rules.

• The size of the design, estimated from the number of transistors in the design
and the layout design rules.

• Attention to transistor-level placement and interconnect to implement
logic gates.

• Careful floorplanning and architecture definition to minimize area and maximize
performance. These leaf cells are potentially used thousands of times,
so the extra effort in achieving area savings for each cell is justly rewarded
in the finished chip.

• Careful design of the power supply implementation. This also includes
consideration of substrate and tub contacts. If this is done well, the power
supply routing and bulk connection requirements of an entire block or chip
can be met by building these requirements into the design of the leaf cells.

• Attention to the design of the interface to other cells. As mentioned previously,
these leaf cells may be used many, many times, and area savings can
be achieved by minimizing the overhead required to place two leaf cells adjacent
to each other. Ideally, leaf cells should be designed to abut directly to
all possible cells that may be placed adjacent to them.


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  1. admin


  2. guru

    Layout of a Hierarchical Design

    Guidelines for the Layout of a Hierarchical Design

    • Develop and use a floorplan plan. This cannot be emphasized enough, and
    it should be done at all levels of layout design.

    • Define the hierarchy of a design in the planning stage. There are no hardand-
    fast rules for defining the hierarchy of a design, but common sense
    is hard to beat. Common guidelines for determining different levels of
    hierarchy include the following:
    Circuits that are to be instantiated many times need to be cells
    Divide designs into functional or area-specific blocks
    Divide designs into blocks that allow multiple designers in parallel to
    work on them
    If symmetrical layout is desired, use a single half cell and mirror it to
    complete the design
    The use of hierarchy is discussed in many areas throughout the book.
    • Develop and obey standards for layout near the boundary of a cell. The
    floorplan and the type of cell that is being implemented should define how
    the cell should interface to its neighbors. The interface requirements of any
    design should be known and understood in the planning stage.

    Use template cells to define global characteristics—cell dimensions and
    the placement of power supplies and wells are good candidates to define
    the interface of the cell. Consistent use of templates ensures that all cells
    conform to a standard and will integrate together smoothly.
    Assume that a boundary interface is fixed—if any polygon is required to
    cross the boundary of the cell, then the floorplan at a higher level in the
    design needs to be consulted before it is allowed. This avoids overlapping
    polygons with those that are unseen.
    Half design rule approach—if the cell is to abut to itself or other cells with
    similar boundary conditions, then a correct-by-construction approach
    would be to ensure that all internal polygons are spaced away from the
    boundary by a value that is half the specific design rule. In this way, when
    the cell abuts to another cell, spacing rules will not be violated.
    Verify the cell with its neighbors—this technique guarantees that the cell is
    correct in all cases.