# band gap reference

### Techniques for bipolar band gap voltage reference

** Layout Problems **

Bad cross-coupling. As in a good op-amp, the critical transistors should be laid out with cross-coupling — example, 1/2 of Q1 on one side of Q2 and the other half on the other side of Q2, so the centroid of Q1 and of Q2 will be at the same place. Likewise, critical resistors should be arranged so that 1/2 of R1 is on one side of R2, and the other half on the other side — again, common centroid. This is especially important in a power regulator where large temperature gradients can be expected. Also it is very advantageous to reject gradients in sheet rho, beta, etc. In a typical band-gap, this cross-coupling should be done for the delta-Vbe transistors and also for the PNP transistors that serve as their collector loads, unless you can prove it to be unnecessary.

Layout of Delta-Vbe circuit vs. Vbe. In some circuits, the transistors that form the delta-Vbe are not the same ones that make the Vbe. These must be laid out to reject gradients from all expected directions.

Thermal regulation errors. When a band-gap regulator or reference has a step change of dissipation, the thermal gradients across the die may cause significant errors. A good layout with adequate cross-coupling and attention to detail is normally required to keep these errors to acceptable levels. A good power regulator can do 0.005%/W; a good precision reference can do 0.002%/W. Thoughtful layout techniques as mentioned above are especially important for a library cell that will be used in an ASIC, because when it is used, you can never guess where the thermal gradients will come from; you have to lay the circuit out to reject gradients from all directions.

Rejection of I x R drops in power busses. If some parts of a circuit are connected to a power bus at one point, and other parts at another point, significant errors can be caused when current flows through the bus. In some cases, you can specify that no such current can flow through the bus; in cases where the bus current must be expected to fluctuate, the connections to the power bus must be arranged to reject the I x R drops.

Thermal stress in corners of the die. When a precision circuit is laid out far off the center-line of the die, near a corner, the thermal stresses can cause errors. For best results, avoid putting precision circuits in corners or far off-axis. This applies to ASIC cells, of course.

**Start-up Circuit Problems **

Bad start-up. Normally applies only to series-mode circuits, not shunt-mode.

Start-up circuit too weak. This often happens when the start-up current (high-value resistor or EPI-FET) puts out too little current. This problem is often exacerbated by high temperatures, leaky diodes, leaky capacitors, or excessive substrate currents if one of the terminals is pulled below the substrate. You can never absolutely be free of this, but you can avoid it if you have a good start-up test. Do not expect the computer to be of much help.

Start-up circuit too strong. This can happen when the EPI-FET puts out too much current and overwhelms the start-up circuit. It’s not easy to model this in SPICE, but you can think about this as a worst-case to be avoided.

Dynamic start-up with no dc start-up. The circuit can start on the dv/dt of the input, but may not start if dv/dt is small. Use a start-up test.

Start-up too slow. You may avoid this by good worst-case design and good modelling in SPICE or breadboarding.

**Oscillations **

Oscillation due to capacitive load. You avoid this by good circuit design. Sometimes the condition can be helped by pre-load currents, or by a series R-C damper network to ground. Use Pease’s Principle to make sure that ringing is not lurking nearby which will turn into oscillation when you turn your back. Check for ringing at all relevant temperatures.

Oscillations at some temperatures and not others. Check for this by watching the Vout for ringing as the part’s temperature is SWEPT from one extreme to the other. Note, monitoring the dc output voltage is not necessarily sufficient to insure freedom from oscillation.

Oscillations due to improper start-up circuit. Make sure the start-up circuit is well-designed and well-behaved in all worst cases.

Oscillations because the breadboard had enough strays but the IC does not. This is a matter of good modelling. The breadboard can be expected to lie about this. SPICE may be helpful if applied thoughtfully.

Obscure oscillations. The computer often lies badly about these. It may refuse to admit that they happen, and refuse to show them happening.

**DC Output Voltage Errors (Room temp) **

Excessively broad distribution of Vref. When you expect a tolerance of ±3% and the observed distribution is excessive, the problem is usually either badly-matched resistors or transistors. The geometries must be identical as drawn and as masked. If your small resistor is short, your large resistor should be made of a group of short resistors. Sometimes it is advantageous to draw the Rs and Qs as cells, so that the mask-making process acts identically on each cell.

Parts cannot be trimmed. Make sure that every voltage can be trimmed by at least one combination of trims; avoid any possible “holes” in your trim scheme.

Interaction of trims. It is a good idea to make sure that in your plan, the size of each trim is (substantially) invariant of whether any of the previous trims have been done.

Dependence of pre-trim Vref on beta. In general, a higher beta transistor has a lower Vbe. In some designs, a pinch resistor (whose resistance is a linear function of beta) is used to compensate for the shift of Vbe and improve the room-temp accuracy. In other cases, a pinch resistor is used to compensate for tempco, even as it degrades the room-temp accuracy.

Band-gap “narrowing”. With high-speed processes, the band-gap voltage (and the voltage for zero tempco) is decreased vs. ordinary transistors. A good breadboard can help determine the right place to operate. The computer cannot.

**Low-voltage-lock-out problems.**

YOU must engineer carefully to get good results at low voltages, as the system may require good behaviour at very low supply voltages, and the reference may not want to give it. The breadboard works better than SPICE, here. Check at all temperatures.

Thermal limit circuit works badly, poor errors, soft knee. Try to use a circuit that has been successful in the past. Hysteresis is often a good feature.

High noise due to starvation. Be sure to check the breadboard.

High noise due to high resistance. Check the breadboard carefully, and use realistic transistor samples. High-beta parts will have higher rbb’ than low-beta ones.

Bad matching due to buried layer. If the actual buried layer causes crystal growth to fall in the middle of a critical transistor, Vbe matching may suffer. Note, the crystal growth at the surface is shifted from where the buried layer appears to be.

Saturation due to insufficient buried layer. Transistors do not run well at warm temperatures when asked to run near saturation, especially at high temp, when the buried layer has been omitted.

Assembly shift. This is usually caused by stress sensitivity. A good layout can help minimize this.

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