asic interview 2
did you had any rectilinear macros if so any thing special you did during floor-plan
did your chip had multi-vt flow , yes or no
if multi-vt how did you managed using it in synthesis
what is the extraction process
what are the various IO’s like PCI/SPI/SDIO/USB/….
how many STA modes did you had
did you run functional STA and Test STA
did you balance test clocks
did you chip test works on atspeed or low speed
what is your scan-shift frequency
how many test-modes do you have
do you test analog macros during test
do you have jtag mode
how many plls do you have
do you have fractional pll’s as well
do you have DSP in your chip
what are the various protocols used in your chip
what is the maximum bus frequency in your chip
do you have multiple masters and multiple slaves accessing your chip bus
how did your bus arbitration logic work
21) Define what is meant by the terms design rules checking, layout versus schematic, and electrical rules check?
Are all three procedures required in every chip design?
22) What is meant by the term “porosity”?
Why is it desirable for a cell or macro to have high porosity?
23) What are the main differences in priorities between microprocessor design, ASIC design, and memory design?
How are those differences reflected in the corresponding design flows?
24) What is an “application-specific memory”, according to Clein?
What are some specific examples of this part type?
25) What is the difference between a soft IP block (soft core) and a hard IP block (hard core)?
– most flexible
– exist either as a gate-netlist or RTL.
– best for plug and play
– less portable and less flexible.
– physical manifestations of the IP design.
26) In ASIC design, what are the main advantages of expressing the design using a hardware description language, such as VHDL or Verilog?
The main reason for using high level hardware design like VHDL or Verilog is easy generating hundred of million gate counts chip better than schematic entry design.
27) Why are memory layouts designed primarily from the bottom up, instead of from the top down, like other ICs?
With respect to a memory layout, what is meant by “array efficiency”?
29) What is “pitch-limited layout”?
What are some of the major circuits in a memory layout that must meet pitch-limited constraints?
30) What are some of the typical kinds of cells that one would expect to find in a library of standard cells?
31) The layout of standard cells is constrained to simplify the job of place & route tools. Give several examples of these constraints.
32) Why did older cell libraries include so-called feed through cells?
Why are such cells no longer required in cell libraries for modern processes?
33) What is electro migration?
How does electro migration affect the design of a standard cell based design?
34) What is a gate array?
Why are main advantages of using gate arrays to implement an IC?
What are some of the main disadvantages, with respect to custom design or standard cell based design?
35) Why might one want to use some gate array based design inside an otherwise custom IC design, according to Clein’s experience?
36) What are some of the major similarities and differences of standard cells and datapath cells?
37) How is the problem of driving a clock node different from that of designing a regular signal node?
What are the key goals when laying out a clock node?
What is a “pad frame”?
What are “staggered” pads?
39) Why are 90 degree corners usually avoided in the layout of pad cells?
40) In the layout of output pad driver transistors, why is the gate length often lengthened at both ends of the gate?