asic and cad

ASIC, Custom and cell-based designers are using CAD software from either Cadence, Synopsys, Mentor Graphics, Aldec, Synplicity etc to aid them in the design of their circuits and architectures.

In the custom design flow, designers usually enter a schematic of their architecture and then they simulate it in order to observe the designs’ behavior under certain process characteristics within a specific technology node (eg 90nm, 65nm etc).

In order to observe secondary effects they can even draw the mask layout of the design and simulate again. Finally, in order to fabricate the chip they still use the CAD software to assist them in the design flow of the chip. Without the CAD software the design flow would be longer, more tedious, more error prone. In today’s fast time-to-market industry this is totally unacceptable.

In the stardard-cell based design designers usually enter an HDL code (VHDL or Verilog) and the CAD software picks up the cells from a cell library when simulating and synthesizing the design. Usually a 1st prototype is downloaded into an FPGA board for a quick check of the idea.

Verification techniques can also be applied through the CAD softwares to ensure the proper functionality of the design.

Today, even higher level languages are used (its more like pure programming) to simulate a higher-level architectural design such as SystemC and SystemVerilog.

No ASIC design can be done without using CAD tools from the industry. Big companies have their internal CAD division to produce the tools which support their IP. Most of ASIC companies depend upon THIRD PARTY companies which supplies all the CAD software.
This include like SYNOPSYS, MENTOR, to name few in field.

At each stage of ASIC design you need various tools like for SYNTHESIS you need DESIGN COMPILER and for placement you need placer tool like ICC/PHYSICAL COMPILER and timing tool to do static timing analysis like PRIMETIME/ etc.
For routing and PHYSICAL verification you need the tools. Again they come form the third party.

This is when you are designing in ASIC and large design CBD. IF you are using FPGA then XILINX provide most of the tools.


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