Anti-jitter circuits (AJCs) are a class of electronic circuits designed to reduce the level of jitter in a regular pulse signal. AJCs operate by re-timing the output pulses so they align more closely to an idealised pulse signal. They are widely used in clock and data recovery circuits in digital communications, as well as for data sampling systems such as the analog-to-digital converter and digital-to-analog converter. Examples of anti-jitter circuits include phase-locked loop and delay-locked loop. Inside digital to analog converters jitter causes unwanted high-frequency distortions. In this case it can be suppressed with high fidelity clock signal usage.
An anti-jitter circuit has an integrator storage capacitor (C3). A charge pump (C1, D1, D2) derives from an input pulse train at least one charge packet during each cycle of the input pulse train and supplies the charge packets to the storage capacitor (C3). A controlled current sink (T1) operating in conjunction with a high impedance low pass filter (R1, C4) continuously discharges the storage capacitor (C3) to create a sawtooth voltage waveform (Op2) having a mean d.c. voltage level (Op3). A differential comparator compares the sawtooth voltage waveform (Op2) with the mean d.c. voltage level (Op3) and the comparator output is used to trigger a monostable circuit to generate an output pulse train having reduced time jitter.
The Anti-Jitter circuit suppresses the phase and time jitter on a frequency source by feed-forward cancellation automatically balanced over a wide range of source frequencies. The balance is maintained by a ‘DC-removal’ feedback control loop that results in a lowest base-band (or sideband) jitter suppression frequency for the AJC and a consequential limitation on the final settling speed for the phase error. In this paper an ‘analytic AJC system simulator’, written in Mathcad is used to find some ‘optimum’ sets of AJC control loop parameters. The AJC transfer functions for ‘jitter suppression’ and for the filtering of the two main noise sources, ‘integrator noise’ and ‘comparator noise’, are derived from the AJC system block diagram. Then for typical values of the two noise sources the total predicted output noise spectrum and the suppression ratio are plotted in a format suitable for comparison with measured noise and suppression results from a spectrum analyser. By integration of the predicted noise spectra the Mathcad simulator also can produce estimates for the total jitter limit of the AJC internally generated noise. These confirm that the AJC close-to-carrier noise (inside the loop bandwidth) is much less than for a typical PLL of the same bandwidth (because there is no division in the AJC). For an AJC (discharge) current of 1 mA the further out sideband noise corresponds to a VCO with a Q of about 5 to 10; with an increase of equivalent Q to 50 to 100 if the discharge current is raised to 10 mA.