Design Rule Check (‘DRC’) provides assurance that the design and layout of a device are compatible and will not lead to device failure during normal operation or production of the device. The analysis process which led to the modification of the corporate CMOS7 antenna DRC rules and device layout for the ‘Super I/O’ device will be discussed. Failures were generated during Early Failure Rate (‘EFR’) reliability stress which were found to be related to Yield failures. Failure analysis results indicated these failures were all on specific transistors in one circuit cell. This revelation led to the modification of the corporate DRC run set on antenna rule. Slight changes to the product layout were also made to follow the modified rule. The reliability and yield failures were eliminated.
The ‘Antenna Effect’
Modern fabrication flows use plasma etching as an integral part of some process steps. The plasma etching systems create and sustain an energized and highly ionized state of matter in order to etch or deposit layers onto silicon wafers. As a result of this exposure, charges can build up on circuit areas. Ion implant equipment can also cause charge build up. Uncontrolled discharge of these charges may cause permanent physical damage to the physical structures on the device, e.g., transistor gate oxide.
‘Antenna’ and ‘Antenna Ratio’
The propensity for damage to the circuitry on a wafer can be exacerbated by the existence of ‘antenna’ structures. The ‘antenna’ is an interconnect, i.e., a conductor like polysilicon or metal, that is not electrically connected to silicon, i.e., not ‘grounded’, during the processing steps of the wafer. The connection to silicon would normally provide an electrical path to bleed-off any accumulated charges. If the connection to silicon does not exist, charges and may build up on the interconnect to the point at which rapid discharge does take place and permanent physical damage results, e.g., to MOSFET gate oxides. This destructive phenomenon is known as the ‘antenna effect’.
The ‘antenna ratio’ of an interconnect is used to predict if the antenna effect will occur. ‘Antenna ratio’ is defined as the ratio between the physical area of the conductors making up the antenna to the total gate oxide area to which the antenna is electrically connected. A higher ratio implies a greater propensity to fail due to the antenna effect. This can result either from a relatively larger area to collect charge or a reduced gate oxide area on which the charge is concentrated.
A number of techniques can be utilized to minimize the antenna effect. For example, the occurrences of antennas can be predicted and their ratios calculated using design verification and layout software known as ‘design rule check’ (‘DRC’) programs. Then by adjusting the physical layout of the interconnects, the antenna ratios can be reduced to an acceptable level. A ratio of 100:1 is a typical design rule upper limit. In addition, processing steps utilizing plasma can be optimized to reduce the build-up of charges on any antennas that do exist on devices.
via national semiconductor.