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anaconda the analog layout


Overview Most of the time and effort in analog physical design is spent on the tedious detail work at the device, wire and polygon level. Many final instances of circuit and layout share a similar topology and are differentiated only by device parameters and second-order geometric details. Most of the time, to design a new cell, topologies do not need to be created but rather preserved and reused while geometry details are tweaked and refined for each specific circuit. Examples include manually re-sizing devices and wires again and again in order to match certain output loads, or migrating the design to other processes, meeting symmetry and matching requirements. Automation applied to these geometry modifications can have a major impact on overall analog design productivity. Anaconda allows designers to reuse existing layout topologies and implement modified device parameters and design constraints from a schematic – minimizing layout time and effort. Figure 1 illustrates the impact of Anaconda on the overall analog design cycle. By migrating an initial design to create a new baseline topology in the target technology and then shortening the refinement time for each derivative design, Anaconda users can accelerate analog physical design time by a factor of three or more. By maintaining a pre-determined and welldesigned layout topology, Anaconda provides a controlled mechanism to accelerate layout – yielding results with the predictability and quality of handcrafted layout. Furthermore, Anaconda is seamlessly integrated into the Cadence®Virtuoso® schematic and layout environment. Anaconda can be used immediately to augment and accelerate existing flows and methodologies whether traditional analog layout





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