adc veriloga model


module top;
wire in, clk, out;
ideal_adc i1(in,clk,out);
endmodule
module ideal_adc(in,clk,out);
input in,clk;
output [0:adc_size-1] out;
voltage in,clk,out;
parameter integer adc_size = 8 from [1:inf);
parameter real fullscale = 1.0;
parameter real delay_ = 0, trise = 10n, tfall = 10n;
parameter real clk_vth = 2.5;
parameter real out_high = 1, out_low = 0 from (-inf:out_high);
real sample,thresh;
real result[0:adc_size-1];
integer i;
analog
begin
@(cross(V(clk)-clk_vth, +1))
begin
sample = V(in);
thresh = fullscale/2;
for(i=adc_size-1;i>=0;i=i-1)
begin
if (sample > thresh)
begin
result[i] = out_high;
sample = sample – thresh;
end
else result[i] = out_low;
sample = 2*sample;
end
end
V(out) < + transition(result,delay_,trise,tfall); end endmodule DAC model
module ideal_dac(in,out);
input [0:dac_size-1] in;
output out;
voltage in,out;
parameter real dac_size = 2 from (1:inf);
parameter vth = 2.5;
parameter real trise = 0 from [0:inf);
parameter real tfall = 0 from [0:inf);
real code;
integer pow2 [0:dac_size];
analog
begin
@(initial_step)
for (i=0;i< =dac_size;i=i+1) pow2[i] = pow(2,i); code = 0; for (i=0;i vth) ? pow2[i] : 0;
V(out) <+ transition(code/pow2[dac_size],0,trise,tfall); end endmodule