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ADC and DAC Introduction

With the recent shift towards digital information processing, low power A/D conversion has evolved as a key requirement in many electronic systems.
Especially in portable applications, restrictions on the available power or energy tend to dictate a stringent upper bound for the maximum affordable energy per A/D conversion.

While feature size scaling has enabled the possibility of implementing extremely fast ADCs in standard CMOS technology , the resulting power dissipation at these technology limits is often prohibitively high. In modern applications, where the power budget is typically only a fraction of a Watt, power efficiency rather than technology speed upper bounds ADC throughput.

Over the past decade, tremendous progress has been made in reducing ADC power dissipation. Hence, one is tempted to ask: Are we approaching “fundamental” limits? How much more improvement can we hope for? These questions are difficult to answer with great precision, what is possible in today’s technology.

An ADC inputs an analog electrical signal such as voltage or current and outputs a binary number. In block diagram form, it can be represented as such:

ADC

A DAC, on the other hand, inputs a binary number and outputs an analog voltage or current signal. In block diagram form, it looks like this:

ADC

Together, they are often used in digital systems to provide complete interface with analog sensors and output devices for control systems such as those used in automotive engine controls:

ADC

It is much easier to convert a digital signal into an analog signal than it is to do the reverse. Therefore, we will begin with DAC circuitry and then move to ADC circuitry.

Basics of DAC and ADC more details

Books on A/D and D/A Converters and analog integrated circuit

CMOS Mixed Signal Circuit Design, R. Baker.
CMOS Circuit Design, Layout, and Simulation.
Continuous-Time Sigma Delta Modulation for A/D Conversion,
Oversampling A/D Converters
Continuous-Time Delta-Sigma Modulators
Design of Multi-bit Delta-Sigma A/D Converters,
Systematic Design for Optimization of Pipelined ADCs, Kluwer
CMOS Data Converters for Communications, Gustavsson, , Kluwer

Integrated Converters, Jespers, Oxford, with MATLAB toolbox.
Modular CMOS A/D Converters, Lin,
Top-Down Design of High-Performance Sigma-Delta Modulators, Medeiro, Kluwer
High-Speed A/D Converters, Moscovici, Kluwer
Delta-Sigma Data Converters, Norsworthy, Shrier, and Temes,
The Design of Low-Voltage Sigma-Delta Modulators by Rabii and
Wooley,
Principles of Data Conversion System Design by Behzad Razavi.
Data Converters for Wireless Standards, Shi, Kluwer
Integrated A/D and D/A Converters, Van de Plassche,
Circuit Techniques for A/D Converters, Waltari, Kluwer
Design of Analog-Digital VLSI Circuits, Prentice Hall,

Books on General Analog Design and Layout
Design Criteria for Low Distortion Op Amps, , Kluwer

Huijsing, Operational Amplifiers, Theory and Design, Kluwer
CMOS, BiCMOS, and Bipolar Operational Amplifiers, deLangen, Kluwer,
Eschauzier, Frequency Compensation of Operational Amplifiers, Kluwer
The Art of Analog Layout, by Alan Hastings.
CMOS Analog Circuit Design, Allen, Oxford,
Analog BiCMOS Design, Daly, CRCPress,
On-Chip ESD Protection for Integrated Circuits, Wang, Kluwer
Trade-offs in Analog Circuit Design,Toumazou et al,Kluwer.
Analog Circuit Design, Michelle Steyaert et al, Kluwer.
Analysis and Design of Analog Integrated Circuits, Gray & Meyer, Wiley
CMOS Mixed-Signal Circuit Design, Baker,
Basic ESD and I/O Design, Dabral, Wiley.
ESD in Silicon Integrated Circuits, Amerasekera, Wiley.





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  1. ADC Expert

    RECENT applications of analog/digital converters (ADC’s) are increasing in digital data reading fields, for example, hard disk drives (HDD’s), digital video disks, and local-area networks . These applications need highspeed and low-error-rate operation. Short latency is also very important for HDD applications that have feedback loops . In spite of a large number of elements, the flash architecture is one of the best solutions for high-speed operation and is also the best for short latency. A pipeline architecture has advantages in the point of die size; however, it is inferior in latency . Folding ADC’s are very good architectures for high-speed operation and die size; however, their performance degrades with high-frequency analog inputs, and they are prone to environment and process variations , [4]. For consumer applications, production cost and process tolerance cannot be ignored. One of the best solutions for the production costs is mixed-signal systems in CMOS. ADC’s that require fewer extra elements, such as sample-and-hold (S/H) circuits, are preferred, as high-speed CMOS S/H’s operating at more than 100-MHz input bandwidth are difficult to implement and to guarantee over process . Elements such as self-calibrating chopper comparators are suitable for mass production because they have superior tolerance to element mismatches. Chopper comparators have to be autozeroed within a certain period. Ordinary ADC’s with chopper comparators are autozeroed every clock cycle . For some ADC’s converting above 100 MS/s, all comparators are autozeroed at the same time, prior to the comparison, to improve conversion rate, and convert several times with one autozeroing . However, this approach restricts applications because they require an extra autozeroing period. Autozeroing should be done in the background as it enables continuous conversion .

    High-speed ADC’s need to be tolerant of comparator errors, as the probability of comparator error is related to the conversion rate and/or input frequency. On the whole, there are two error-suppression techniques: Gray coding and thermometer code bubble error rejection . Gray coding itself has no correction ability; however, due to the symmetric nature of Gray coding, the difference between the correct code and the incorrect code is small when bubble error occurs. The most critical drawback of Gray coding is converting between Gray and binary codes; this is achieved using serial XOR gates, which add a long delay. Quasi-Gray coding techniques improve the delay of the Gray-to-binary conversion; however, they cannot correct bubble error . Some of the bubble error-rejection techniques implemented at the thermometer code zero-to-one transition detection are able to correct into the same result as the best guess; however, they require a large number of elements. A technique that is implemented after detecting the thermometer code zero-toone transition is twin encoding , but it requires duplicate encoders, resulting in a large number of elements.

  2. Guru

    Acquisition Time – The time required for the sampling mechanism to capture the voltage after the sample command is given for the hold capacitor to charge.
    Conversion Time – The time required for the A/D converter to complete a single conversion once the signal has been sampled.
    Throughput Rate or Samples Per Second (SPS) – The time required for the converter to sample, acquire, digitize, prepare, and output a conversion.
    Integral Non-Linearity (INL) – Specification most relevant to the overall accuracy of the converter. INL is the maximum deviation of a transition point of a conversion to the corresponding transition point of an ideal conversion. INL represents cumulative DNL errors.
    Differential Non-Linearity (DNL) – The error in width between output conversion codes. The maximum deviation in code width from the ideal 1 LSB code width (FSR/2^n). DNL errors of less than –1 correspond to a missing code.
    Missing Code – The situation where an A/D converter will never output a specified code regardless of the input voltage.
    Monotonic – Implies that an increase (or decrease) in the analog input voltage will always produce no change or an increase (or decrease) in output code. Monotonicity does not imply that there are no missing codes.
    Bipolar vs. Unipolar Output – Differential converters give a bipolar output corresponding to positive and negative numbers. The binary output scheme is usually two’s complement. A unipolar output corresponding to a positive output, from 0 to VREF.






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