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vlsi interview question 1


1. What happens if Vds is increased over saturation?

2. In the I-V characteristics curve, why is the saturation curve flat or constant?

3. What happens if a resistor is added in series with the drain in a mos transistor?

4. What are the different regions of operation in a mos transistor?

5. What are the effects of the output characteristics for a change in the beta (ß)
6. value?

7. What is the effect of body bias?

8. What is hot electron effect and how can it be eliminated?

9. What is latchup problem and how can it be eliminated?

10. What is channel length modulation?

11. What is the effect of temperature on threshold voltage?

12. What is the effect of temperature on mobility?

13. What are the different types of scaling?

14. What is stage ratio?

15. What is charge sharing on a bus?

16. What is electron migration and how can it be eliminated?

17. Can both pmos and nmos transistors pass good 1 and good 0?

Explain.
18. Why is only nmos used in pass transistor logic?

19. What are the different methodologies used to reduce the charge sharing in
20. dynamic logic?

21. What are setup and hold time violations?

How can they be eliminated?

22. Explain the operation of basic sram and dram.
23. Of Read and Write operations, which ones take more time?

Explain.
24. What is meant by clock race?

25. What is meant by single phase and double phase clocking?

26. If given a choice between NAND and NOR gates, which one would you pick?

Explain.
27. What are stuck-at faults?

28. What is meant by ATPG?

29. What is meant by noise margin in an inverter?

How can you overcome it?

30. Why is size of pmos transistor chosen to be close to three times of an nmos
31. transistor?

32. Explain the origin of the various capacitances in the mos transistor and the
33. physical reasoning behind it.
34. Why should the number of CMOS transistors that are connected in series be
35. reduced?

36. What is charge sharing between bus and memory element?

37. What is crosstalk and how can it be avoided?

38. Two inverters are connected in series. The widths of pmos and nmos transistors of
39. the second inverter are 100 and 50 respectively. If the fan-out is assumed to be 3,
40. what would be the widths of the transistors in the first inverter?

41. In the above situation, what would be the widths of the transistors if the first
42. inverter is replaced by NAND and NOR gates?

43. What is the difference between a latch and flip-flop?

Give examples of the
44. applications of each.
45. Realize an XOR gate using NAND gate.
46. What are the advantages and disadvantages of Bi-CMOS process?

47. Draw an XOR gate with using minimal number of transistors and explain the
48. operation.
49. What are the critical parameters in a latch and flip-flop?

50. What is the significance of sense amplifier in an SRAM?

51. Explain Domino logic.
52. What are the differences between PALs, PLAs, FPGAs, ASICs and PLDs?

53. What are the advantages of depletion mode devices over the enhancement mode
54. devices?

55. How can the rise and fall times in an inverter be equated?

56. What is meant by leakage current?

57. Realize an OR gate using NAND gate.
58. Realize an NAND gate using a 2:1 multiplexer.
59. Realize an NOR gate using a 2:1 multiplexer.
60. Draw the layout of a simple inverter.
61. What are the substrates of pmos and nmos transistors connected to and explain the
62. results if the connections are interchanged with the other.
63. What are repeaters in VLSI design?

64. What is meant by tunneling problem?

65. What is meant by negative biased instability and how can it be avoided?

66. What is Elmore delay algorithm?

67. What are false and multi cycle paths?

68. What is meant by metastability?

69. What are the various factors that need to be considered while choosing a
70. technology library for a design?

71. What is meant by clock skew and how can it be avoided?

72. When stated as 0.13µm CMOS technology, what does 0.13 represent?

73. What is the effect of Vdd on delay?

74. What are the various limitations in changing the voltage for less delay?

75. What is the difference between testing and verification?

76. While trying to drive a huge load, driver circuits are designed with number of
77. stages with a gradual increase in sizes. Why is this done so?

What not use just one
78. big driver gate?

79. What is the effect of increase in the number of contacts and vias in the
80. interconnect layers?

81. How does the resistance of the metal layer vary with increasing thickness and
82. increasing length?

83. What is the effect of delay, rise and fall times with increase in load capacitance?

84. In a simple inverter circuit, if the pmos in the Pull-Up Network is replaced by an
85. nmos and if the nmos in the Pull-Down Network is replaced by a pmos transistor,
86. will the design work as an non-inverting buffer?

Justify your answer.

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COMMENT Uncategorized



  1. Mansoor

    When stated as 0.13µm CMOS technology, what does 0.13 represent?

    0.13µ is the minimum channel lenght available in that particular technology. In sense we cant get a MOS with less than 0.13µ gate lenth in this technology.We can get more than 0.13µm .

  2. Guru

    It is the channel length

  3. Vijay chhabra

    When stated as 0.13µm CMOS technology, what does 0.13 represent?

    • Viva

      Thanks for the comment I just noeictd it and would like to reply. I am not sure where you see drive currents roughly half those in the VLSI paper . I do not recall the author discussing the SRAM transistors in the paper you refer to, he discussed the SP/MP/HP transistor versions. It is not unusual for nano-probed transistors to have a measured Idsat a little lower than conference reported transistors, there are a few factors that cause this. Probe contact resistance is one we estimate that with ~200ohm contact resistance will reduce Idsat by ~2-3% due to lowering Vg, other factors are estimate of gate width (For i FinFet we assume twice fin height but can only measure physical fin height (Not fin height from dopant interface) and of course we may not be comparing apples to apples, we have the benefit/drawback of measuring a few transistors from one die in millions produced we do not know where in the distribution it lies compared to the data presented at the conference







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