ELECTRONICS COMPONENTS SALES AND SERVICE

RTL register-transfer level DESIGN DEVELOPMENT TESTING


register-transfer level (RTL) is a design abstraction which models digital circuit

Power reduction through RTL clock gating
free download

ABSTRACT This paper describes a design methodology for reducing ASIC power consumption through use of the RTL clock gating feature in Synopsys Power Compiler. This feature causes inactive clocked elements to have clock gating logic automatically inserted

Efficient sequential ATPG for functional RTL circuits
free download

Abstract We present an efficient register-transfer level automatic test pattern generation (ATPG) algorithm. First, our ATPG generates a series of sequential justification and propagation paths for each RTL primitive via a deterministic branch-and-bound search

C-based Interactive RTL Design Methodology
free download

Abstract Much effort in RTL design has been devoted to developingpush-buttontypes of tools. However, given the highly complex nature of RTL design, interactive design space exploration with assistance of tools and algorithms can be more effective. In this report, we

Seismicity pattern changes prior to large earthquakes-An approach of the RTL algorithm
free download

A statistical method, which is called the Region-Time-Length ( RTL ) algorithm and takes into account information such as magnitude, occurrence time and place of earthquakes, was applied to earthquake data to investigate seismicity pattern changes prior to large

Methodology for repeater insertion management in the RTL layout, floorplan and fullchip timing databases of the Itanium microprocessor
free download

Page 1. 99 Methodology for Repeater Insertion Management in the RTL Layout, Floorplan and Fullchip Timing Databases of the Itanium Microprocessor Rory McInerney Kurt Leeper Troy Hill Intel Corp. Intel Corp. Intel Corp. SC12-408 SC12-405 RA2-350Intel Corp. Intel Corp. Intel

Red thermoluminescence ( RTL ) in volcanic quartz: development of a high sensitivity detection system and some preliminary ndings
free download

Abstract: As part of a general study exploring the suitability of the RTL of quartz for dating volcanic events, a modied RisaI Reader apparatus has been assembled and tested. Modication consisted of an alternative, cooled photomultiplier, and the incorporation of

RTL Coding Styles That Yield Simulation and Synthesis Mismatches
free download

ABSTRACT This paper details, with examples, Verilog coding styles that will cause a mismatch between preand post-synthesis simulations. Frequently, these mismatches are not discovered until after silicon has been generated, and thus require the design to be re-

Formal verification of floating-point RTL at AMD using the ACL2 theorem prover
free download

Abstract-We describe a methodology for the formal verification of the correctness, including IEEE-compliance, of register-transfer level models of floating-point hardware designs, and its application to the floating-point units of a series of commercial microprocessors produced

RTL : reduced texture spectrum with lag value based image retrieval for medical images
free download

Abstract Medical images have become the recent key investigation tools for medical diagnosis and treatment planning. Due to the advent of digital imaging the need of data storage and retrieval of medical images increased rapidly. Some difficulties in retrieving the

Optimized RTL design and implementation of LZW algorithm for high bandwidth applications
free download

Abstract. This paper presents a high-speed low-complexity Register Transfer Logic ( RTL ) design and implementation of the lossless Lempel-Ziv-Welch (LZW) algorithm on Xilinx Virtex II device family for High Bandwidth Applications. Comparative analysis of the

RTL emulation: the next leap in system verification
free download

To answer the second question, semiconductor fabrications can now put millions of logic gates on a single chip using deep sub-micron technology. This rapid increase in the complexity of chips and systems has outstripped traditional verification techniques. This is

Guest editors introduction: RTL to GDSII-from foilware to standard practice
free download

University of California, San Diego ically correct or 100% layout-rule correct if it doesnt meet timing constraints. Traditionally, static timing analysis was run at the beginning of the process at a milestone called RTL handoff, and at the end of the flow at a mask sign-off

Automatic generation of fault tolerant VHDL designs in RTL
free download

Abstract Fault Tolerance (FT) is an important issue in electronic devices. Detecting and even correcting internal faults during normal operation makes possible the usage of these circuits in critical applications. FT has been taken into account for many years during design process

A FSM extractor for HDL description at RTL level
free download

Abstract Due to the increasing complexity of modern circuit designs, HDL based design methodology is getting popular. Because Finite State Machines (FSMs) and datapaths have significantly different properties, dealing them with two different ways is a trend of many CAD

Characteristics of seismicity patterns prior to the M 5 earthquakes in the Koyna Region, Western India-application of the RTL algorithm
free download

Method The analysis of earthquake data is performed using the well established method known as RTL algorithm (Sobolev and Typukin, 1997; Huang et al., 2001) which uses the three parameters called R (region around the earthquake epicenter), T (time) and L (rupture

RTL Implementation of Viterbi Decoder using VHDL
free download

Abstract: Forward Error Correction techniques are utilized for correction of errors at the receiver end. Convolutional encoding is an FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by additive white Gaussian noise

A hybrid approach for equivalence checking between system level and RTL descriptions
free download

ABSTRACT In this paper we present a hybrid method to check the equivalence between an algorithmic specification in C (ASC) as a golden model and RTL implementation in Verilog ( RTL ). This method is able to look for equivalent nodes automatically without needs for

MDG tools for the verification of RTL designs
free download

Although ROBDDs [1, 2] have proved to be a powerful tool for automated hardware verification, they require a Boolean representation of the circuit. Since the size of an ROBDD grows, sometimes exponentially, with the number of Boolean variables, ROBDD-based

Preferable use of red-thermoluminescence ( RTL )-dating for quartz extracts from archaeologically burnt potterycomparison of RTL and BTL (blue-TL)
free download

Abstract Red-( RTL ) and blue-thermoluminescence (BTL) dating procedures for quartz aliquots were applied to nine Jomon pottery pieces, which were manufactured and used 3,500-6,000 years ago. Quartz grain extracts from each piece were measured with respects

Automatic and Optimized Generation of Compiled High-Speed RTL Simulators
free download

Abstract In this paper we focus on the derivation of optimal code when generating high- speed event-driven compiled simulators for processor architectures described on register transfer level ( RTL ). The simulators generation is part of a framework, which aims at

X-propagation woes: masking bugs at RTL and unnecessary debug at the netlist
free download

Abstract:: This paper presents a complete and practical methodology to comprehensively solve the X problem in RTL design. It begins by reviewing common sources of Xs, and describes how they cause functional bugs as well as unwarranted debug that prolong

Assertion-Based Verification with PSL Integrated with an Existing RTL Verification Environment
free download

S Maisniemi, J Kalinainen- PSL/SUGAR Consortium Meeting DATE, 2004 212.199.43.83 AbstractThe purpose of this paper is to describe the bene-fits and drawbacks of the property specification language (PSL) in assertion-based verification (ABV). Both simulation based and static verification methods are considered. PSL can be utilized to complement the

Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs.
free download

Abstract. In this paper C-Slow Retiming (CSR) on RTL is discussed. CSR multiplies the functionality of cores by adding the same number of registers into each path. The technique is ideal for FPGAs with their already existing registers. Previously publications are limited to

The Wilberforce pendulum: a complete analysis through RTL and modelling
free download

The Wilberforce pendulum is a didactical device often used in class demonstration to show the amazing phenomenon of coupled oscillations (rotational and longitudinal) producing beats in a special mass-spring set up. The phenomenon is particularly surprising

Buffer minimization in RTL synthesis from coarse-grained dataflow specification
free download

Abstract-This paper concerns area-efficient automatic hardware architecture synthesis and its optimization from dataflow graph (DFG) specification for fast HW/SW cosynthesis. A node in a DFG represents a coarse grain computation block such as FIR and DCT and a port in a

A fast area-delay estimation technique for RTL component generators
free download

Abstract An important bene t of high-level synthesis is rapid design space exploration through examination of di erent design alternatives. However, such design space exploration is not feasible without fast and accurate area and delay estimates of the

RTL guided random-pattern-resistant fault detection and low energy BIST
free download

Abstract: The purpose of this paper is to present a methodology for low-energy BIST, in which a loosely deterministic test pattern is generated using RTL functional description. Using the high correlation property between n-detection of RTL faults and single detection of

On the non-scan BIST schemes under power constraints for RTL data paths
free download

Abstract This paper proposes three non-scan BIST schemes for RTL data paths and formulates DFT problems for the schemes under power constraints. The proposed schemes include one generic non-scan BIST scheme where we can explore trade-offs among

Systemverilog in use: First rtl synthesis experiences with focus on interfaces
free download

ABSTRACT In this paper we describe some of our experiences from bringing SystemVerilog 3.1 and DesignCompiler 2003.12 together. A number of important SystemVerilog RTL elements are discussed, and the SystemVerilog interface construct is exercised in-depth

Sequential Logic Synthesis with Retiming in Encounter RTL Compiler (RC)
free download

Abstract Typical ASIC designs are highly unbalanced with respect to the timing criticality of their combinational logic paths. This is mainly due to the ad-hoc manual design specification of the register transfer level ( RTL ), which does not use any information regarding the

A DFT method for RTL data paths achieving 100% fault efficiency under hierarchical test environment
free download

Abstract In this paper, we propose a DFT method for RTL data paths to achieve 100% fault efficiency. The DFT method is based on hierarchical test and usage of a combinational ATPG tool. The DFT method requires lower hardware overhead and shorter test generation

C-based RTL design framework for processor and hardware-IP synthesis
free download

Abstract Although high-level synthesis tools and processor synthesis tools have emerged to improve the design productivity of SoC components, we have yet to see a practical solution for the challenging tasks of system-level integration and verification of these individual

Mutation based debugging technique with auto-correction mechanism for RTL designs
free download

AbstractVerification and debugging are important phases in System on Chip (SoC) design flow where a large amount of time and effort must be spent to ensure the correctness of the SoC designs. Although many Computer Aided Design (CAD) solutions have been provided

A DFT method for functional scan at RTL
free download

AbstractF-scan, a novel design-for-testability (DFT) method for high-level description of circuits, provides an effective alternative to current scan-based DFT approaches. By optimally utilizing available functional elements and paths for test, hardware overhead is

Stir bar sorptive extraction (TWISTERTM) RTLCGC-MS. A versatile method to monitor more than 400 pesticides in different matrices (water, beverages, fruits
free download

SUMMARY The performance of stir bar sorptive extraction (SBSE) for enrichment of pesticides from different matrices is discussed. Emphasis is on vegetables, fruits and baby food because this is much more challenging than enrichment from aqueous samples. By

Specifying instructions semantics using λ- RTL (interim report)
free download

Abstract The Zephyr project is part of an effort to build a National Compiler Infrastructure, which will support research in compiling techniques and high-performance computing. Compilers work with source code, abstract syntax, intermediate forms, and machine

RTL power estimation and optimization
free download

Useful for:-Design exploration.-Design validation/signoff.Cycle-accurate RTL description:- Statements of the HDL synthesizable subset.-Limited accuracy: Resources are not instantiated.Structural RTL description:-Interconnection of data-path blocks (adders,

An approach for verification assertions Reuse in RTL test pattern generation
free download

Abstract Assertions are used in functional verification of design to detect design errors. In this paper we propose an approach for their reuse in manufacturing test pattern generation at Register-Transfer Level ( RTL ) for nonscan designs. The proposed approach provides for

Design and implementation of high speed Baugh Wooley and modified booth multiplier using cadence RTL
free download

Abstract Modified Booth Multiplier is one of the different techniques for signed multiplication. It is used normally as the fastest multiplier. Baugh Wooley Multiplier is another technique for signed multiplication. It is not widely used because of its complexity of its structure. Here

Writing VHDL for RTL synthesis
free download

The name VHDL is representative of the language itself: it is a two-level acronym that stands for VHSIC Hardware Description Language; VHSIC stands for very high speed integrated circuit. The language is vast, verbose, and was originally designed for modeling digital

A New Approach for Accurate RTL Power Macro-Modeling
free download

AbstractRegister transfer level power macro-modeling is well known as a promising technique for accurate and efficient power estimation. This paper proposes effective approaches based on the tablebased method for the RTL power macro-modeling. The new

Method for automatic generation of RTL in VHDL using decision diagrams
free download

ABSTRACT In recent years, decision diagrams have earned a prominent place in the field of logic design as means of efficient representation of switching function, in terms of needed storage space and processing complexity, especially for the tasks of design, testing and

RTL Logic Realization Using Ladder Diagram For Programmable Controller
free download

ABSTRACT: Ladder diagram is a widely used Graphical Programming Language for Programmable Controllers. The design of Programmable Controller using Ladder Diagrams is an experience-based method and verification is typically done through experiments or

HWML: RTL /Structural Hardware Description using ML
free download

Abstract This paper describes how functional programming techniques can be used to obtain simple, compact and highly expressive hardware descriptions even for complex designs. We use the functional programming language ML to describe the hardware

Consistent SystemC and VHDL code generation from State Charts for virtual prototyping and RTL synthesis
free download

AbstractIn todayhardware development, SystemC code is widely used for virtual prototyping, where an abstract system model is used to do an early exploration of the hardware implementation as well as software development. The synthesis tools, on the other

ConPro: Rule-Based Mapping of an Imperative Programming Language to RTL for Higher-Level-Synthesis Using Communicating Sequential Processes
free download

The ConPro programming language, an new enhanced imperative programming language is mapped to Register-Transfer-Logic using a higher-level-synthesis approach performed by the synthesis tool ConPro. In contrast to other approaches using modified existing software

Capo: congestion-driven placement for standard-cell and RTL netlists with incremental capability
free download

In this chapter, we describe the robust and scalable academic placement tool Capo. Capo uses the min-cut placement paradigm and performs (a) scalable multiway partitioning,(b) routable standard-cell placement,(c) integrated mixed-size placement,(d) wire length-driven

Physical-Aware, High-Capacity RTL Synthesis for Advanced Nanometer Designs
free download

Page 1. Sanjiv Taneja Vice President, Product Engineering Cadence Design Systems Physical-Aware, High-Capacity RTL Synthesis for Advanced Nanometer Designs Page 2. Agenda 1. Market trend and challenges 2. Physical effects of interconnect and congestion 3. Physical

Economical Antenna Reception Design for Software Defined Radio using RTLSDR
free download

Abstract The field of wireless communication has become the hottest area and Software Defined Radio (SDR) is revolutionizing it. By bringing much functionality as software, SDR reduces the cost of hardware maintenance and up-gradation. Open source hardware such

High-Level vs. RTL Com binational Equivalence: An Introduction
free download

Page 1. High-Level vs. RTL Com binational Equivalence: An Introduction Alan J. Hu University of British Columbia Page 2. 2 OutlineMotivation, Problem StatementGate-Level Equivalence VerificationSymbolic SimulationCutpointsSymbolic Simulation of a High-Level Model

Bridging the gap between abstract RTL and bit-level designs
free download

Abstract System-ML is a framework, embedded in the Ocaml programming language, for describing synchronous hardware designs. Using system-ML, one describes a hardware design at the RTL level using Hawk-style polymorphic, synchronous streams to represent

RTL Low Power Techniques for System-On-Chip Designs
free download

ABSTRACT Low power design remains a complex and critical challenge for System-On- Chip (SOC) designs which often involve the reuse of existing internal and/or external Intellectual Property (IP), while often incorporating new IP as well. This approach to IC

An approach to RTL false path mapping using uniqueness of paths
free download

AbstractInformation on false paths in a circuit is useful for design and test. Since identification of the false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence

A Practical Guide to Deploying Assertions in RTL
free download

Abstract: With the recently growing interest in assertion-based formal analysis tools, we are reminded again that RTL designers have a large role to play in creating assertions for their designs. After a brief review of the typical taxonomy of assertions, this session walks RTL

An approach for data propagation from Tree SSA to RTL
free download

Abstract This paper describes an approach for propagation of information collected during Tree SSA optimization passes to RTL level to enable RTLpasses to take advantage of the information available on Tree SSA, which is generally more precise than that available on

Seamless Refinement from Transaction Level to RTL Using SystemVerilog Interfaces
free download

ABSTRACT The need for high-performance functional simulation of large system-on-chip designs, especially when the behavior of software is to be modeled in simulation, has given rise to a range of behavioral modeling styles that are often collectively known as transaction

Abstracting RTL designs to the term level
free download

Abstract Term-level verification is a formal technique that seeks to verify RTL hardware descriptions by abstracting away details of data representations and operations. The key to making term-level verification automatic and efficient is in deciding what to Abstract We

A synthesis postprocessor for fully morphable RTL datapaths
free download

AbstractReconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware. In this paper, a special type of course grain

Who Put Assertions In My RTL Code And Why How RTL Design Engineers Can Benefit from the Use of SystemVerilog Assertions
free download

ABSTRACT There are engineers (but not you once you read this paper) who say that assertions are for verification that should only be written by verification engineers and bound, rather than embedded, into RTL design code. This misconception short changes the

A non-scan DFT method at RTL based on fixed-control testability to achieve 100% fault efficiency
free download

Abstract This paper proposes a non-scan design-for-test- ability method for register-transfer level circuits where a cir- cuit consists of a controller and a data path. It achieves com- plete fault efficiency with low hardware overhead and at-speed testingWith the advance in semiconductor

ELECTRONICS COMPONENTS SALES AND SERVICE-INTEGRATED CIRCUIT-ANALOG, DIGITAL, DSP, RF IC, WIRLESS IC, VLSI, CAPACITOR, RESISTOR, INDUCTOR, PCB, MODULE, SENSOR