DSP (digital signal processing) on FPGA – Let’s see the advantages and disadvantages!

First let?s see the maximum speed that can be achieved by the processing scheme. Well, the
answer is given by a simple rule: the maximum speed of a chain is imposed by the slowest
link, which is the ADC. The commercial ADCs sampling rate is limited to 250MSample/sec
(for example Linear Technology). Of course you can find ADC having 10GSamples/sec
throughput, but can you afford it? The Nyquist sampling theorem says the sampling
frequency should be at least 2 times higher than the highest frequency component in the
sampled signal, but in practice oversampling is recommended. So the analog signal that can
be filtered has the maximum frequency component around 25 MHz. This is way enough for
home appliance or educational applications. Usually the digital to analog conversion is not a
concern; the DACs can work at higher rates than the ADCs.
FPGAs are highly flexible circuits that can work at high frequencies, but the most important
thing is the possibility of parallel processing. Sounds promising, but to accomplish digital
filtering is a long process, requiring digital filter design knowledge and working experience
with FPGA.
Unlike DSPs, the FPGA doesn?t have incorporated ADC nor DACs. The designer?s task is to
connect the conversion devices to the FPGA by implementing some buffer zone most likely in
HDL (VHDL or Verilog). The most of the stand alone ADCs have an industry standard
protocol as an integrated interface, like SPI or I2C. Some engineers will get lucky and they
will use IP cores that are already written and tested. But for sure some will have to write their
own interfaces. This task seems to be a routine work; theoretically the interface is a big state
machine, what everybody can make in few days. Problems will appear when you have to
make the interface compatible with DMA controllers or you have to connect to an industry
standard bus, you never heard about. Do not be scared! Digital filter, as FIR or IIR,
implementation doesn?t need sophisticated interfacing with converters.
Now let?s focus on some digital filter design issues. Digital filters are working at a defined
sampling frequency. My recommendation is to choose the ADC?s and the filter?s sampling
frequency equal. In this case only continuous data flow and data integrity must be assured.
One can see that the ADC interface must provide the samples at a constant rate. The
samples than are processed by the digital filter. To compute the coefficients of the digital filter
many filter design applications can be used. Another big difference between the DSPs and
FPGAs arise, because usually the filter?s coefficients are real, not integer, values. The DSPs
can work with floating point representation, easing the computation of the filter response.
Also on FPGAs the use of floating point cores is possible, but it will take up huge area inside

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