asic interview 4

application specific integrated circuit interview questions and answers

66) What is the purpose of minimum area design rules?

67) What is the purpose of end overlap rules?

6Cool What is the phenomenon of latch-up?

Why is it a serious concern in CMOS layout design?

69) Describe six different layout strategies that are commonly used to minimize the possibility of latch-up.

70) Why is it wise to plan designs to make it easier to change details later?

71) What is meant by metal strap programmability and via programmability?

Give one example where each techniques is commonly used.

72) What is the difference between test pads and probe pads?

73) Dan Clein advocates the use of contact and via cells, which is not a common design practice. What are his reasons?

74) In which situation should one avoid using the minimum allowed feature sizes allowed by the design rules?

75) What fundamental factors limits the speed with which detected design errors can be corrected?

76) When floor planning a chip at the start of the IC layout process, what are the main goals in deciding how to arrange the major blocks in the design?

power line, noise, clock tree?


77) How is block floor planning different from chip floor planning?

78 What is a silicon compiler?

79) What is the difference between a channel router and a maze router?

Which type of router will tend to produce higher utilization factors?

80) What is a chip assembly tool?

What kind of routing should a chip assembly tool provide to have maximum flexibility?

81) At IBM, it has been found to be advantageous to sacrifice performance when migrating a chip design in one process into a second process. Process migration is facilitated by the use of “migratable design rules”. What is the major benefit that can be obtained by such rules to offset the loss in potential chip performance?

82) At IBM a design methodology has been developed that makes the layout of standard cells very similar to that of gate array cells. What is the potential benefit of intermixing such cells in the same chip design?

83) In its ASIC design flow, IBM uses a formal verification tool that performs a technique called Boolean equivalence checking. What is the primary potential benefit of using formal verification methods in design verification?

What is the conventional way of verifying the equivalence of different implementations of the same function?

84) IBM has standardized its logic design on the use of pulse-triggered latches, whereas the rest of the industry has tended to adopted design based on edge- triggered flip-flops. What is the strategy that IBM has adopted to be able to accommodate designers from other companies who wish to have ASICs fabricated through IBM?

85) Why are terminator cells sometimes used when clock trees are inserted into a block of placed standard cells?

86) When constructing a clock tree with distributed buffers, why is it very desirable to keep the buffers lightly loaded near the root of the clock distribution tree?

Why can leaf nodes of the clock tree can be loaded more heavily?

Why does one aim to have a balanced clock tree?

87) What is the difference between two- and three-dimensional analysis of interconnect capacitance.

8Cool Guard bands are usually built into the timing estimates employed by logic synthesis, cell placers, and other CAD tools. What is lost when the guard bands are relatively large?

What could be gained if the timing estimates could be made more accurate?

89) Full 3-D capacitance calculations are generally extremely timing consuming. How can the technique of tunneling be used to make such calculations efficient enough to use in large IC designs?

89) The output of a 3-D field solver is a charge distribution over the signal net under consideration, and a charge distribution over the surrounding passive nets. Generally the signal net is assumed to be at a potential of 1 volt while the other nets are held at 0 volts. How can the signal net’s self-capacitance and coupling capacitance then be computed?

90) Moore’s Law predicts a doubling in the number of transistors per chip every two to three years. The major factor supporting Moore’s Law is improvements in lithographic resolution that permit finer features. What are the two other major factors that Moore believes have allowed Moore’s Law to hold?

Even if physical factors allow for further increases in per-chip component density,
what other factors could slow or even stop Moore’s Law in practice?

91) What is meant by the term “dual damascene process”?

How has the availability of this type of process simplified the creation of multiple interconnected
metal layers?

92) In processes that have multiple layers of metal interconnect, why is it common to make the upper wires thicker than the lower layers?

(The use of fat wires is sometimes called “reverse scaling”.) In which situations would one be willing to use reverse scaling and hence appear to throw away the possible advantages of thinner wires?

93) What are some of the important reasons why DRAM technology has been a pioneer for semiconductor technology advances?

94) Briefly explain what are planar DRAM cells, trench capacitor DRAM cells, and stacked capacitor DRAM cells. Which type of cell is becoming dominant in embedded DRAMs?

Why is this so?

95) There are numerous technological challenges and additional costs with embedded DRAM. Describe three of the main potential advantages that could be gained with embedded DRAM. What are characteristics of an application that could benefit from using embedded DRAM?

96) What are the three most common process solutions to providing embedded DRAM?

Discuss some of the important trade-offs that must be made when selecting a process strategy for embedded DRAM.

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