asic interview 3

application specific integrated circuit interview questions and answers

41) Why is the pad ring provided with power supply connections that are separate from those of the core design?

42) What are so-called friendly cells in a DRAM core design?

Why and where these cells included in a memory design?

43) Why are metal straps used along with polysilicon wordlines in memory designs?

44) Why are wordline driver circuits very long and narrow?

45) Describe some of the alignment keys that are included in IC layouts.

46) Why is the power supply interconnect layout layout planned out before other elements?

Similarly, why are busses, differential signals, and shielded signals routed before other general signals?

47) What are the root and resistance styles of power supply layout?

4Cool What are some of the main reasons why clock skew minimization is such a major design challenge?

49) What are the major advantages and disadvantages of using a single clock tree conductor driven by one big buffer?

50) In ASIC design flows, why are clock trees inserted after the logic cells have been placed?

In such clock trees, how is clock skew minimized at the
leaves of the tree?

51) What is a routing channel?

Why are routing channels used in IC layouts?

52) Why is the estimated area for routing channels increased by 10% during early stages of layout planning?

53) When routing a signal interconnect, why is it desirable to minimize layer changes through vias?

54) Interconnect resistance is usually minimized in IC layouts. Give at least four situations where a deliberably large, but controlled, resistance is usually required?

55) Why should minimum-width paths be avoided in the design of deliberate resistances?

56) Usually one wishes to minimize the capacitance of electrical nodes in an IC design. Give four examples of circuits where one would wish a larger, but controlled, capacitance at a node?

57) The capacitance on a node is the sum of several components. What is meant by fringe capacitance?

How does reducing the width of a conductor affect the fringe capacitance?

5Cool How can the parasitic capacitance between two signal nodes possibly cause the signal transition on one of the nodes to be unexpectedly sped up?

59) How can a layout designer help ensure that the propagation delay along two conductors is very similar?

By running the two traces side by side and making them of equal length.

60) List four situations where it may be desirable to have 45 degree corners in the interconnect.

61) Explain what is meant by electromigration. What are some possible consequences of unexpectedly high electromigration?

How is electromigration
controlled in IC layout design?

62) Why are wide metal conductors, such as those in the power rings, provided with slits?

What constraints must be followed when positioning these slits?

63) When placing multiple vias to connect two metal conductors, why is it better to space the vias far apart from each other?

64) Why would a DRAM layout be verified against two or more different sets of design rules?

65) What is the antenna effect, and how can it cause problems in an IC design?

What are two layout techniques that can be used to reduce vulnerability to the
antenna effect?

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