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ADC ANALOG TO DIGITAL CONVERTER DESIGN DEVELOPMENT TESTING


converts an analog signal into a digital signal. ADCs receive analog input, perform calculations on the analog signal, and then digitally encode the output in a format that computerized systems can process. Analog-to-digital converter chips are used in a variety of applications

In vivo measurement of ADC change due to intravascular susceptibility variation
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METHODS Imaging was performed at 2.0 Tesla on a smallbore, GE Omega CSI system, using a 50 mm diameter home-built birdcage coil, and Acustar imaging gradients. Rat brain images were generated using a 40 mm FOV, 64 samples x 32 phase-encode steps, 2 NEX,

Vehicle emissions and driving cycles: comparison of the Athens driving cycle ( ADC ) with ECE-15 and European driving cycle (EDC)
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ABSTRACT Vehicle emissions constitute the main source of atmospheric pollution in modern cities. The increasing number of passenger cars, especially during the last decade, resulted in composite traffic problems with serious consequences on emissions and fuel

Aperture uncertainty and ADC system performance
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Aperture uncertainty is a key ADC concern when performing IF sampling. The terms aperture jitter and aperture uncertainty are synonymous and are frequently interchanged in the literature. Aperture uncertainty is the sample-to-sample variation in the encoding process. It

Which ADC architecture is right for your application
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Most ADC applications today can be classified into four broad market segments:(a) data acquisition,(b) precision industrial measurement,(c) voiceband and audio, and (d) high speed (implying sampling rates greater than about 5 MSPS). A very large percentage of

Future-ready ultrafast 8bit CMOS ADC for system-on-chip applications
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Semiconductor technology is now approaching 100 nanometer feature size and will soon be below 100 nanometer. This technology trend presents new challenges in analog-digital mixed signal circuit design. A mixed signal circuit must be integrated on a single chip along

8-GSA/S 8-bit ADC system
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Abstract We report on an analog to digital converter ( ADC ) system with 8 bit resolution and a sample rate of 8 GSa/s. The system is composed of 2 thick-film hybrid substrates, each holding a silicon bipolar ADC chip and a custom CMOS memory chip. Each ADC chip

ADC input noise: the good, the bad, and the ugly. Is no noise good noise
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Input-referred Noise (Code-Transition Noise) Practical ADCs deviate from ideal ADCs in many ways. Inputreferred noise is certainly a departure from the ideal, and its effect on the overall ADC transfer function is shown in Figure 1. As the analog input voltage is increased,

Adc architectures iii: Sigma-delta adc basics
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The sigma-deltaADC is the converter of choice for modern voiceband, audio, and highresolution precision industrial measurement applications. The highly digital architecture is ideally suited for modern fine-line CMOS processes, thereby allowing easy addition of

Mixed- ADC Massive MIMO.
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AbstractMotivated by the demand for energy-efficient communication solutions in the next generation cellular network, a mixed- ADC architecture for massive multiple input multiple output (MIMO) systems is proposed, which differs from previous works in that herein one-bit

DesignImplementation of Low Power 3-bit Flash ADC in 0.18m CMOS
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AbstractThis paper describes the design and implementation of a Low Power 3-bit flash Analog to Digital converter ( ADC ). It includes 7 comparators and one thermometer to binary encoder. It is implemented in 0.18 um CMOS Technology. The pre-simulation of ADC is

A CMOS low power, quad channel, 12 bit, 40MS/s pipelined ADC for applications in particle physics calorimetry
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Abstract The AD41240 is a 12-bit, four-channel pipelined analog to digital converter fabricated in a rad-tolerant CMOS technology and capable of running at 40 MHz with a power consumption per channel of 150 mW at 2.5 V. The converter core uses a 10 stages

The operation of the SAR- ADC based on charge redistribution
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All Texas Instruments TLV-and TLC-series sequential serial analog-to-digital converters perform successive approximation based on charge redistribution. This article explains the operation of the SAR (successive approximation register)- ADC (analog-to-digital converter).

An empirical approach to finding energy efficient ADC architectures
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AbstractThe problem of selecting an optimally efficient ADC architecture at different resolutions is treated using a mainly empirical approach. By analyzing a large amount of measured performance data reported in the literature, the power efficiency of different ADC

Comparison of Apparent Diffusion Coefficient ( ADC ) with Histologic Cellularity in Breast Tumors [J]
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Lucas-Quesadaand our previous studies [1, 2] showed that the ADCs of benign and malignant breast lesions were different and measuring the ADCs of focal breast masses was useful for characterizing the masses. But the overlap in ADC between benign and malignant

A low-power column-parallel 12-bit ADC for CMOS imagers
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Abstract-This paper describes the design of a low-power column-parallel single-slope ADC for CMOS imagers. The design exploits the characteristics of photon shot noise present in imaging signals to reduce power consumption. A prototype imager with a 12-bit column-

Mathematical and computer models in multi-pass ADC design and optimization
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Abstract The paper presents a mathematically grounded approach to the analysis and optimisation of multi-pass analogue-to-digital converters (MADCs) with the algorithmic forming the estimates of converted samples. The approach enables a comprehensive

ADC histogram test using small amplitude input waves
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Abstract: The experimental investigation on a histogram test for analog-to-digital converters (ADCs) using as stimulus signals small-amplitude triangular waves superimposed to variable DC levels is presented. The test allows inexpensive triangular generators to be

ADC based measurements: A common basis for the uncertainty estimation
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Abstract-In the last years, many Authors have dealt with the uncertainty evaluation of the measurement performed by using an analog-to-digital converter, proposing different approaches to analyze the uncertainty propagation. However, in these studies, in order to

Progress in the development of a superconductive high-resolution ADC
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AbstractThis paper is a progress report on the development of a high-resolution analog-to- digital converter ( ADC ) which uses a phase modulation/demodulation architecture. Presented are an analysis of the performance limitations, proposed design improvements,

ADC Characterisation using the code density test method with deterministic sampling
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ABSTRACT This paper describes a novel approach for ADC characterisation that uses the code density test method while overcoming the request of a huge number of samples. Instead of collecting samples with a clock frequency uncorrelated with the input test signal,

High-speed ADC building blocks in 90 nm CMOS
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AbstractA samplehold circuit, a comparator and a decision flip-flop are implemented in 90 nm standard CMOS technology. The input switch of the samplehold circuit provides a bandwidth in excess of 30 GHz at a sampling rate of 10 Gs/s. The limiting amplifier based

A new approach to optimization of adaptive ADC with multi-pass residual compensation
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Abstract The aim of the paper is to present a new approach, based on the conception of adaptive fitted observation [1-5], applied to analysis, synthesis and optimization of the structure and parameters of multi-pass compensatory analog-to-digital converters ( ADC )

Statistical performance of Gaussian ADC histogram test
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Abstract In this paper, the statistical properties of the Gaussian Histogram Test (GHT) are theoretically evaluated and compared to the corresponding Cram r-Rao Lower Bound (CRLB). In particular, it is shown that the GHT is asymptotically unbiased and efficient.

Capacitive Touch Using Only an ADC ( CVD )
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This application note describes a new hardware sensing method called Capacitive Voltage Divider (CVD) which uses no external components. It requires only the ADC to perform capacitive touch sensing. The principle is simple, and can be applied to nearly any

Uncertainty in the ADC transition voltages determined with the histogram method
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Abstract This paper, presents an innovative study of the uncertainty in the ADC transition voltages, determined by the Histogram Method for ADC testing. The new approach used, allows for a global and uniform overview of this subject, improving the existing knowledge

fMRI using ADCdependent contrast
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Previous study showed that diffusion weighting can be used to eliminate fMRI signal arised from the vasculature (1). It is thus possible to assess the signal that is crushed due to the diffusion weighting. We investigate the changes of apparent perfusion through the changes

Understanding high speed ADC testing and evaluation
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SNR, SINAD, worst spur, and IMD are tested using a hardware setup similar to that shown in Figure 1. In production tests, the test hardware is highly integrated, but the hardware principles are the same. The basic setup for dynamic testing includes a signal generator,

SAR ADC architecture with digital error correction
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Abstract-This paper describes a high-performance successive approximation (SAR) ADC using three comparators operating in parallel, instead of just one as in conventional ADCs. This comparator redundancy enables higher resolution, potentially faster operation, higher

Measurement of ADC integral nonlinearity via DFT
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Abstract: the paper presents a new methodology, based on the Discrete Fourier Transform of the output, for measuring the integral nonlinearity of an ADC . The new method, unlike the usual histogram test, gives the best polynomial approximation (thesmooth part ) of the AbstractAn improvement of photonic analog-to-digital converter ( ADC ) based on phase- shifted optical quantization (PSOQ) is presented and verified. The resolution can be increased by employing an additional Mach-Zehnder modulator (MZM) to combine with the

Maximum likelihood estimation of ADC parameters from sine wave test data
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Abstract The sine wave test is maybe the most important method for characterizing ADC. By this, the acquisition device is excited with a sinusoidal signal, and a long series of output values is measured. With the help of these observations, the parameters of the DUT can be

Using redundancy to break the link between accuracy and speed in an ADC
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A M-Analog redundancy breaks the link between accuracy and speed in analog circuits. This technique has particular relevance IO analog to digital conversion. As feature size and supply voltage shrink, calibration based on redundancy of flash analog-to-digital converlers

Identification of unified ADC error model by triangular testing signal
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Abstract-Modelling of the integral nonlinearity by the unified behavioural error model expressed as one dimensional image in the code k domain requires a minimal number of the error parameters. The unified error model consists of low and high code frequency

Simple, universal phantom for multi-center apparent diffusion coefficient ( ADC ) measurement
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Quantitative biomarkers are being developed for tumor therapy response assessment where timely assessment of therapy response is extremely important. Diffusion-weighted MR imaging provides such a biomarker, the apparent diffusion coefficient ( ADC ), and there from

X-ray spectroscopy of the ADC source X1822-371 with Chandra and XMM-Newton
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Context. The eclipsing low-mass X-ray binary X1822-371 is the prototype of the accretion disc corona ( ADC ) sources. Its inclination angle ( 82.5°) is high enough that flux from the neutron star is blocked by the edge-on accretion disc. Because the neutron stardirect

Defining and testing dynamic ADC parameters
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77 structed from digital samples, the SNR is the ratio of a root-meansquare (RMS) full-scale analog input to its RMS quantization error, AQUANTIZATION [RMS]= ALSB/(12) 0.5= AREF/(2N (12) 0.5. The RMS value of a sine wave is one-half its peak-to-peak value divided

Analysis of the ADC Method for Direct ODF Calculation by Use of Gauss Models and Standard Functions
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All rights reserved. No part of contents of this paper may be reproduced or transmitted in any www.scientific.net. (#106427537, Google Scholar-17/01/18,20:03:34)

PI A Digital Pixel Image Sensor with 1-bit ADC and 8-bit Pulse Counter in each Pixel
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Abstract We experimentally fabricated an 8-bit full-digital image sensor in which the signals generated in each pixel are directly converted from analog to digital within the each pixel and then output as 8-bit digital signals. Each pixel consists of a photodiode (PD), a 1-bit A/D

Large scale error reduction in dithered ADC
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Abstract: The combination of dithering and correcting table is the way of improvement not only of ADC resolution but also of linearity-effective number of bits. Dithering is used to reduce small-scale errors, such as quantization error, while correcting table reduces large-

ELECTRONICS COMPONENTS SALES AND SERVICE-INTEGRATED CIRCUIT-ANALOG, DIGITAL, DSP, RF IC, WIRLESS IC, VLSI, CAPACITOR, RESISTOR, INDUCTOR, PCB, MODULE, SENSOR