SUCHITAV KHADANGA

CEO, RFIC Technologies
suchitav.khadanga@gmail.com

Suchitav Khadanga (Bangalore, India) is an electronics design engineer having more than 15 years of solid experience in wireless and semiconductor products. Throughout his professional career, he has designed and managed designs from concept to mass production on wireless and broadband RFICs and wireless consumer products which were sold successfully worldwide in million units. He graduated with first class distinction from BU, India, where he studied microelectronics, analog and digital electronics, electromagnetic theory and microwave. After completing research on microelectronics and microwave in CEERI (Central Electronics engineering research institute), Pilani, India he is working in analog and wireless development companies since 1997. In his role he had worked in international locations with companies Intel, NXP, WIPRO. He had successfully completed projects in wireless communication, cellular communication, UWB, WLAN. His main area of work is analog and wireless communication, RFIC, high speed analog, CMOS process. He is currently employed in RFIC technologies, Bangalore, India and working on design, development of next generation wireless products. He is also experienced in preparing and giving professional training courses in RF system design, Analog and RFIC design, VLSI subjects.

He has several research papers and patents on wireless, analog, rfic. he is actively involving in reviewing papers, books on analog, vlsi, rfic and wireless system.

Experience Overview

Have More than 15 years experience in semiconductor industry
Companies
INTEL, bangalore
NXP, Germany
WIPRO, bangalore
Athena Semiconductor, Greece
CEERI, Pilani, India

System design, development and production
Multiband Cellular chip
Wireless communication
UWB Transmitter
Battery management
Frequency Synthesizer
Transreceiver

Circuit Design
Electronics circuits
LNA
VGA VCO, LDO, OPAMP, PFD
Frequency Divider

Layout
Full chip WLAN, GPRS
CMOS Inductor
PAD ring
VCO
LNA

Process and Technology
Cadence, spice, mentor design tool
Semiconductor Device Modeling
CMOS process till 65nm process
tower, tsmc and umc

Additional
Managing chip from system till market
Managing design team
Program Management
Short Term Teaching
Short Term Teaching RFIC
Mentoring junior designers


Frequency Synthesizer design
Client : NXP, Nuremberg Germany
Product: Aero 4223
This is the frequency synthesizer for the quad band transreceiver and designed with TSMC 130nm cmos process technology. The frequency range is 6.5 to 8.5 GHZ. The tank of the vco is combination of fixed capacitor, switched capacitor, varactor and inductors. The design starts with system level analysis and ends with tape out.
Associated with full chip simulation and layout

RFCMOS mixer
Client : NXP, Nuremberg Germany
This is the mixer for the quad band transreceiver and designed with TSMC 65nm cmos process technology. This mixer is in the receiver section of the transreceiver chip.
Mixer Design
Client : Athena Semiconductor (acquired by broadcom), Athens, Greece
Product: ATS 5001
This is mixer in receiver path of quad band receiver. The cmos mixer is double balanced passive mixer initially designed in 0.13 um technology. The design started with analysis of different mixer architectures and after comparison passive mixer had chosen for low power application.

VARIABLE GAIN AMPLIFIER
Client : Athena Semiconductor (acquired by broadcom), Athens, Greece
Product: ATS 2001
This is in base band section of GPRS chip and designed for low noise and low power. This is a two stage amplifier, the first one is fixed low gain and low noise, the second one is an opamp used for changing gain. The frequency is 200Hz to 200 KHz with gain varies from -4 to 26 dB (step size 6dB). The integrated noise is 4nV/sqHz when gain is maximum. The VGA is designed as an independent module and finally integrated in GPRS chip. The VGA design is completed using UMC 0.18um 1.8V process.
1.Mentoring other designers on their design work and reviewing the designs.
2.Involved in characterization of the chips after fabrication of gprs and wlan chip, with test team.

UWB Transmitter design
Client : Intel Bangalore, Bangalore, India
Product: Test Chip (cayman)
The design and development of UWB transmitter is completed. This is transmitter section of UWB transceiver test chip. The power consumption is 50mW only with chip area 200000um2. The transmitted signal varies from 160mV to 800mV with 50ohm load. The frequency range is 3 to 5 GHz with 500 MHz band. It means there are 4 transmitters in this chip. The transmitted signal is hanning shaped with pulse shaper for increasing the bandwidth and more side lobe rejection. The desired requirement is the 10dB bandwidth should not be less than 500MHz and the side lobe should be better than 20 dB as decided by FCC. The result is 10dB bandwidth is 600MHz and side lobe is below 28dB. The pulse shaper is a passive multiplier which multiplies the modulated signal and hanning shaped waveform (generated by a DAC, 20nS period and 5ns pulse width)
Contribution: The work involves analysis of different transmitter architecture and selection of the best architecture in terms of chip area and power consumption. The transmitter was designed from system level to the layout independently with help of one more engineer for layout.

PLL (mixed signal design project)
Company: WIPRO Technology, Bangalore, India
Product: IP Development
Technology Used: TSMC 0.18 um cmos technology and Specter RF from Cadence Tool.
This is a low power dual modulus prescaler PLL having step size 1MHz. except the loop filter all the circuit components are on chip.
Contribution: Design of 2.4GHz VCO, prescaler, programmable divider, phase detector using tsmc 0.18um technology and integration of PLL building blocks.

Low Noise Amplifier Design
Company: WIPRO Technology, Bangalore, India
Product: IP Development
LNA is designed using tsmc 0.18um technology. This is inductively degenerated common source amplifier. . The gain of LNA is 15 dB, noise figure 2.1dB at 2.4GHz frequency having bandwidth 100 MHz, total power consumption is 23mW.


CMOS Operational Amplifier Design (analog design project)
Company: WIPRO Technology, Bangalore, India
Product: IP Development
Technology Used: TSMC 0.25 um cmos technology and Specter RF from Cadence Tool.
Two stages CMOS Operational amplifier is designed using 0.25um cmos technology .The opamp is designed successfully. Gain of opamp is 30K with unity gain 10MHz and power dissipation is 1.9mW.

RF Transistor (design and fabrication of the transistor)
In Central Electronics Engineering Research Institute, Pilani, India
Technology used: In house semiconductor fabrication process and Tanner tools.
The transistors are designed using solving semiconductor device equations and Tanner tools. The optical masks are prepared and transistors are fabricated in millimeter wave devices laboratory of CEERI, Pilani. This work involves design, fabrication and testing of bipolar npn transistor on silicon. Then transistors are packaged in TO-5 package. These devices are tested successfully both in chip and package form. The transition frequency is 2 GHz and the gain is 150~200.
Contribution: a member of the team. Design and characterize the transistors and co-operating in the fabrication process.

RF circuit design
Environment: Millimeter Wave Devices Laboratory of Central Electronics Engineering Research Institute, Pilani, India.
Technology used: In house fabrication process and EESOF from HP.
Few microwave amplifier and microwave oscillator were designed, fabricated and tested using different dielectric substrate. This work involves design, assembly and testing of microwave amplifier (LNA) and microwave oscillators in the 2-3 GHz frequency range on printed circuit board. Finally aluminum package has done to reduce the loss. These circuits are tested successfully and three research papers are presented in national conferences in India.

Wireless Development
Client IBA Dosimetry, Schwarenbruck ,Germany
Developed a solution for wireless and battery solution for replacing existing cables of the instruments for NLOS communication

EDUCATIONAL QUALIFICATION


M. Sc. in Electronics from Berhampur University, orissa, India in 1997
Microelectronics from CEERI, Pilani. Had hands on experience with design tools, semiconductor device, cmos process

RESEARCH PAPERS

"Synchronous programmable divider design for PLL Using 0.18 um RFCMOS technology" IEEE conference in Calgary, Canada

"Development of low phase noise small foot print surface mount VCO" in APSYM-2000, Cochin University, India

"Design and fabrication of low cost Microwave Amplifier" in NCEMDS-99 Gulbarga University, India.

"Design and fabrication of low cost Microwave Oscillator" SWCA-98 Berhampur University,India. Download

Professional Guide

Dr.R.K.Mishra
Dr R.K.Mishra is the professor in department of electronics, where I had studied my masters degree. more details http://bamu.nic.in/electronics/contentRKM/biography.htm


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